1. Technical Field
The embodiments described herein relate to a semiconductor integrated circuit, and, more particularly, to a semiconductor memory apparatus.
2. Related Art
In general, a semiconductor memory apparatus operates by receiving an external voltage. In addition, all internal circuits constituting the semiconductor memory apparatus operate by receiving the external voltage.
As shown in FIG. 1, the semiconductor memory apparatus may include an internal circuit 10, a first voltage supply 20, and a second voltage supply 30.
The internal circuit 10 operates due to a voltage difference between a first voltage node node_1 and a second voltage node node_2.
If an inverted enable signal ‘enb’ is enabled at a low level, the first voltage supply 20 applies an external voltage VDD to the first voltage node node_1.
The first voltage supply 20 includes a first transistor P1. The first transistor P1 includes a gate receiving the inverted enable signal ‘enb’, a source receiving the external voltage VDD, and a drain connected to the first voltage node node_1.
If an enable signal ‘en’ is enabled at a high level, the second voltage supply 30 applies a ground voltage VSS to the second voltage node node_2.
The second voltage supply 30 includes a second transistor N1. The second transistor N1 includes a gate receiving the enable signal ‘en’, a drain connected to the second voltage node node_2, and a source receiving the ground voltage VSS. In this case, the inverted enable signal ‘enb’ has a phase opposite to that of the enable signal ‘en’.
Hereinafter, the operation of the semiconductor memory apparatus having the above structure will be described.
If the inverted enable signal ‘enb’ is enabled, the first supply voltage 20 applies the external voltage VDD to the first voltage node node_1 of the internal circuit 10.
If the enable signal ‘en’ is enabled, the second voltage supply 30 applies the ground voltage VSS to the second voltage node_2 of the internal circuit 10.
The internal circuit 10 is driven by internal current flowing due to a voltage difference between the first voltage node node_1 and the second voltage node node_2.
The typical semiconductor memory apparatus uniformly maintains an amount of current flowing through the internal circuit 10.
If the operational speed of the internal circuit 10 becomes fast, a greater amount of current is consumed. If the operational speed of the internal circuit 10 becomes lowered, a smaller amount of current is consumed. However, in the typical semiconductor memory apparatus, an optimum current is always set for the internal circuit 10 to enable the internal circuit 10 to operate at the maximum speed. This is necessary for allowing the semiconductor memory apparatus to perform both high and low speed-operations.
Accordingly, when the typical semiconductor memory apparatus operates at a low speed, current may be wasted.